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- #ifndef _SFR_H
- #define _SFR_H
- #ifndef __ASSEMBLER__
- #define SFR_RO *(volatile unsigned long const *)
- #define SFR_WO *(volatile unsigned long*)
- #define SFR_RW *(volatile unsigned long*)
- #define SWINT() asm(".long 0xb0030057")
- #define EEBREAKINT() asm(".long 0xb0040057")
- #else
- #define SFR_RO
- #define SFR_WO
- #define SFR_RW
- #define SWINT .long 0xb0030057
- #define EEBREAKINT .long 0xb0040057
- #endif
- #define SFR_BASE 0x00000000
- #define SFR0_BASE (0x00000000 + 0x000)
- #define SFR1_BASE (0x00000000 + 0x100)
- #define SFR2_BASE (0x00000000 + 0x200)
- #define SFR3_BASE (0x00000000 + 0x300)
- #define SFR4_BASE (0x00000000 + 0x400)
- #define SFR5_BASE (0x00000000 + 0x500)
- #define SFR6_BASE (0x00000000 + 0x600)
- #define SFR7_BASE (0x00000000 + 0x700)
- #define SFR8_BASE (0x00000000 + 0x800)
- #define SFR9_BASE (0x00000000 + 0x900)
- #define SFR10_BASE (0x00000000 + 0xa00)
- #define SFR11_BASE (0x00000000 + 0xb00)
- #define SFR12_BASE (0x00000000 + 0xc00)
- #define SFR13_BASE (0x00000000 + 0xd00)
- #define SFR14_BASE (0x00000000 + 0xe00)
- #define SFR15_BASE (0x00000000 + 0xf00)
- //------------------------- SFR Group0 ---------------------------------------//
- #define TICK0CON SFR_RW (SFR0_BASE + 0x01*4)
- #define TICK0CPND SFR_RW (SFR0_BASE + 0x02*4)
- #define TICK0CNT SFR_RW (SFR0_BASE + 0x03*4)
- #define TICK0PR SFR_RW (SFR0_BASE + 0x04*4)
- #define TICK1CON SFR_RW (SFR0_BASE + 0x05*4)
- #define TICK1CPND SFR_RW (SFR0_BASE + 0x06*4)
- #define FUNCMCON0 SFR_RW (SFR0_BASE + 0x07*4)
- #define FUNCMCON1 SFR_RW (SFR0_BASE + 0x08*4)
- #define FUNCMCON2 SFR_RW (SFR0_BASE + 0x09*4)
- #define TICK1CNT SFR_RW (SFR0_BASE + 0x0a*4)
- #define TICK1PR SFR_RW (SFR0_BASE + 0x0b*4)
- #define UART0CON SFR_RW (SFR0_BASE + 0x10*4)
- #define UART0CPND SFR_WO (SFR0_BASE + 0x11*4)
- #define UART0BAUD SFR_RW (SFR0_BASE + 0x12*4)
- #define UART0DATA SFR_RW (SFR0_BASE + 0x13*4)
- #define TMR0CON SFR_RW (SFR0_BASE + 0x14*4)
- #define TMR0CPND SFR_RW (SFR0_BASE + 0x15*4)
- #define TMR0CNT SFR_RW (SFR0_BASE + 0x16*4)
- #define TMR0PR SFR_RW (SFR0_BASE + 0x17*4)
- #define CRSTPND SFR_RW (SFR0_BASE + 0x18*4)
- #define CLKCON0 SFR_RW (SFR0_BASE + 0x19*4)
- #define WDTCON SFR_RW (SFR0_BASE + 0x1a*4)
- #define RTCCON SFR_RW (SFR0_BASE + 0x1b*4)
- #define RTCDAT SFR_RW (SFR0_BASE + 0x1c*4)
- #define CLKCON1 SFR_RW (SFR0_BASE + 0x1d*4)
- #define RTCCPND SFR_WO (SFR0_BASE + 0x1e*4)
- #define SPI0CON SFR_RW (SFR0_BASE + 0x2a*4)
- #define SPI0BUF SFR_RW (SFR0_BASE + 0x2b*4)
- #define SPI0BAUD SFR_RW (SFR0_BASE + 0x2c*4)
- #define SPI0CPND SFR_RW (SFR0_BASE + 0x2d*4)
- #define SPI0DMACNT SFR_RW (SFR0_BASE + 0x2e*4)
- #define SPI0DMAADR SFR_RW (SFR0_BASE + 0x2f*4)
- #define UART1CON SFR_RW (SFR0_BASE + 0x30*4)
- #define UART1CPND SFR_WO (SFR0_BASE + 0x31*4)
- #define UART1BAUD SFR_RW (SFR0_BASE + 0x32*4)
- #define UART1DATA SFR_RW (SFR0_BASE + 0x33*4)
- #define TMR1CON SFR_RW (SFR0_BASE + 0x35*4)
- #define TMR1CPND SFR_RW (SFR0_BASE + 0x36*4)
- #define TMR1CNT SFR_RW (SFR0_BASE + 0x37*4)
- #define TMR1PR SFR_RW (SFR0_BASE + 0x38*4)
- #define TMR2CON SFR_RW (SFR0_BASE + 0x3a*4)
- #define TMR2CPND SFR_RW (SFR0_BASE + 0x3b*4)
- #define TMR2CNT SFR_RW (SFR0_BASE + 0x3c*4)
- #define TMR2PR SFR_RW (SFR0_BASE + 0x3d*4)
- #define CLKGAT2 SFR_RW (SFR0_BASE + 0x3e*4)
- #define DACDIGCON0 SFR_RW (SFR1_BASE + 0x10*4)
- #define DACVOLCON SFR_RW (SFR1_BASE + 0x11*4)
- #define CLKCON4 SFR_RW (SFR1_BASE + 0x1e*4)
- #define USBCON0 SFR_RW (SFR3_BASE + 0x00*4)
- #define USBCON1 SFR_RW (SFR3_BASE + 0x01*4)
- #define USBCON2 SFR_RW (SFR3_BASE + 0x02*4)
- #define USBCON3 SFR_RW (SFR3_BASE + 0x03*4)
- #define USBCON4 SFR_RW (SFR3_BASE + 0x04*4)
- #define PLL0CON1 SFR_RW (SFR3_BASE + 0x15*4)
- #define PWRCON0 SFR_RW (SFR3_BASE + 0x1d*4)
- #define LVDCON SFR_RW (SFR3_BASE + 0x1e*4)
- #define PWRCON1 SFR_RW (SFR3_BASE + 0x1f*4)
- #define PLL1CON1 SFR_RW (SFR3_BASE + 0x22*4)
- #define PLL0DIV SFR_RW (SFR3_BASE + 0x23*4)
- #define PLL1DIV SFR_RW (SFR3_BASE + 0x24*4)
- #define PLL2DIV SFR_RW (SFR3_BASE + 0x25*4)
- #define PLL0CON SFR_RW (SFR3_BASE + 0x26*4)
- #define PLL1CON SFR_RW (SFR3_BASE + 0x27*4)
- #define PLL2CON SFR_RW (SFR3_BASE + 0x28*4)
- #define XO26MCON SFR_RW (SFR3_BASE + 0x29*4)
- #define CLKCON2 SFR_RW (SFR3_BASE + 0x2a*4)
- #define RSTCON0 SFR_RW (SFR3_BASE + 0x2b*4)
- #define CLKGAT0 SFR_RW (SFR3_BASE + 0x2c*4)
- #define LPMCON SFR_RW (SFR3_BASE + 0x2d*4)
- #define MEMCON SFR_RW (SFR3_BASE + 0x2e*4)
- #define CLKCON3 SFR_RW (SFR3_BASE + 0x2f*4)
- #define PWRCON2 SFR_RW (SFR3_BASE + 0x38*4)
- #define CLKGAT1 SFR_RW (SFR3_BASE + 0x3f*4)
- #define HSUT0CON SFR_RW (SFR3_BASE + 0x30*4)
- #define HSUT0CPND SFR_RW (SFR3_BASE + 0x31*4)
- #define HSUT0BAUD SFR_RW (SFR3_BASE + 0x32*4)
- #define HSUT0DATA SFR_RW (SFR3_BASE + 0x33*4)
- #define HSUT0TXCNT SFR_RW (SFR3_BASE + 0x34*4)
- #define HSUT0TXADR SFR_RW (SFR3_BASE + 0x35*4)
- #define HSUT0RXCNT SFR_RW (SFR3_BASE + 0x36*4)
- #define HSUT0RXADR SFR_RW (SFR3_BASE + 0x39*4)
- #define HSUT0FIFOCNT SFR_RW (SFR3_BASE + 0x3a*4)
- #define HSUT0FIFO SFR_RW (SFR3_BASE + 0x3b*4)
- #define HSUT0FIFOADR SFR_RW (SFR3_BASE + 0x3c*4)
- #define HSUT0TMRCNT SFR_RW (SFR3_BASE + 0x3d*4)
- #define PICCONCLR SFR_WO (SFR4_BASE + 0x0c*4)
- #define PICCONSET SFR_WO (SFR4_BASE + 0x0d*4)
- #define PICENCLR SFR_WO (SFR4_BASE + 0x0e*4)
- #define PICENSET SFR_WO (SFR4_BASE + 0x0f*4)
- #define PICCON SFR_RW (SFR4_BASE + 0x10*4)
- #define PICEN SFR_RW (SFR4_BASE + 0x11*4)
- #define PICPR SFR_RW (SFR4_BASE + 0x12*4)
- #define PICADR SFR_RW (SFR4_BASE + 0x13*4)
- #define PICPND SFR_RW (SFR4_BASE + 0x14*4)
- #define FMRXDGTCON0 SFR_RW (SFR5_BASE + 0x07*4)
- #define FMRXANGCON0 SFR_RW (SFR5_BASE + 0x18*4)
- #define PLL2CON1 SFR_RW (SFR3_BASE + 0x0d*4)
- #define SADCDAT0 SFR_RO (SFR5_BASE + 0x20*4)
- #define SADCDAT1 SFR_RO (SFR5_BASE + 0x21*4)
- #define SADCDAT2 SFR_RO (SFR5_BASE + 0x22*4)
- #define SADCDAT3 SFR_RO (SFR5_BASE + 0x23*4)
- #define SADCDAT4 SFR_RO (SFR5_BASE + 0x24*4)
- #define SADCDAT5 SFR_RO (SFR5_BASE + 0x25*4)
- #define SADCDAT6 SFR_RO (SFR5_BASE + 0x26*4)
- #define SADCDAT7 SFR_RO (SFR5_BASE + 0x27*4)
- #define SADCDAT8 SFR_RO (SFR5_BASE + 0x28*4)
- #define SADCDAT9 SFR_RO (SFR5_BASE + 0x29*4)
- #define SADCDAT10 SFR_RO (SFR5_BASE + 0x2a*4)
- #define SADCDAT11 SFR_RO (SFR5_BASE + 0x2b*4)
- #define SADCDAT12 SFR_RO (SFR5_BASE + 0x2c*4)
- #define SADCDAT13 SFR_RO (SFR5_BASE + 0x2d*4)
- #define SADCDAT14 SFR_RO (SFR5_BASE + 0x2e*4)
- #define SADCDAT15 SFR_RO (SFR5_BASE + 0x2f*4)
- #define WKUPCON SFR_WO (SFR5_BASE + 0x39*4)
- #define WKUPEDG SFR_WO (SFR5_BASE + 0x3a*4)
- #define WKUPCPND SFR_WO (SFR5_BASE + 0x3b*4)
- //------------------------- SFR Group1 ---------------------------------------//
- #define AUBUFDATA SFR_RW (SFR1_BASE + 0x01*4)
- #define AUBUFCON SFR_RW (SFR1_BASE + 0x02*4)
- #define AUBUFSTARTADDR SFR_RW (SFR1_BASE + 0x03*4)
- #define AUBUFSIZE SFR_RW (SFR1_BASE + 0x04*4)
- #define AUBUFFIFOCNT SFR_RW (SFR1_BASE + 0x05*4)
- #define AUBUF1DATA SFR_RW (SFR1_BASE + 0x06*4)
- #define AUBUF1CON SFR_RW (SFR1_BASE + 0x07*4)
- #define AUBUF1STARTADDR SFR_RW (SFR1_BASE + 0x08*4)
- #define AUBUF1SIZE SFR_RW (SFR1_BASE + 0x09*4)
- #define AUBUF1FIFOCNT SFR_RW (SFR1_BASE + 0x0a*4)
- #define AUBUFPEAKLEFT SFR_RW (SFR1_BASE + 0x0b*4)
- #define AUBUFPEAKRIGHT SFR_RW (SFR1_BASE + 0x0c*4)
- #define DACDIGCON0 SFR_RW (SFR1_BASE + 0x10*4)
- #define DACVOLCON SFR_RW (SFR1_BASE + 0x11*4)
- #define AU0LMIXCOEF SFR_RW (SFR1_BASE + 0x12*4)
- #define AU0RMIXCOEF SFR_RW (SFR1_BASE + 0x13*4)
- #define AU1LMIXCOEF SFR_RW (SFR1_BASE + 0x14*4)
- #define AU1RMIXCOEF SFR_RW (SFR1_BASE + 0x15*4)
- #define DACRMDCCON SFR_RW (SFR1_BASE + 0x16*4)
- #define DACDCEXP SFR_RW (SFR1_BASE + 0x17*4)
- #define PHASECOMP SFR_RW (SFR1_BASE + 0x18*4)
- #define SRC0VOLCON SFR_RW (SFR1_BASE + 0x19*4)
- #define SRC1VOLCON SFR_RW (SFR1_BASE + 0x1a*4)
- #define SDDACBFCON SFR_RW (SFR1_BASE + 0x1b*4)
- #define SDDACBFKICK SFR_RW (SFR1_BASE + 0x1c*4)
- #define SDDACBFCOEF SFR_RW (SFR1_BASE + 0x1d*4)
- #define CLKCON4 SFR_RW (SFR1_BASE + 0x1e*4)
- #define SPFCON1 SFR_RW (SFR1_BASE + 0x1f*4)
- #define AUCON0 SFR_RW (SFR1_BASE + 0x20*4)
- #define AUCON1 SFR_RW (SFR1_BASE + 0x21*4)
- #define AUCON2 SFR_RW (SFR1_BASE + 0x22*4)
- #define AUCON3 SFR_RW (SFR1_BASE + 0x23*4)
- #define AUDMAADR SFR_RW (SFR1_BASE + 0x24*4)
- #define SPFCON0 SFR_RW (SFR1_BASE + 0x25*4)
- #define SPFDAT SFR_RW (SFR1_BASE + 0x26*4)
- #define SPFDMAADR SFR_RW (SFR1_BASE + 0x27*4)
- #define SPFPND SFR_RW (SFR1_BASE + 0x28*4)
- #define SPFCPND SFR_RW (SFR1_BASE + 0x29*4)
- #define SPFRATE SFR_RW (SFR1_BASE + 0x2a*4)
- #define AUANGCON6 SFR_RW (SFR1_BASE + 0x2c*4)
- #define AUANGCON4 SFR_RW (SFR1_BASE + 0x2d*4)
- #define AUANGCON5 SFR_RW (SFR1_BASE + 0x2e*4)
- #define SDADCGETDCCON SFR_RW (SFR1_BASE + 0x2f*4)
- #define SDADCDMACON SFR_RW (SFR1_BASE + 0x30*4)
- #define SDADCDMACLR SFR_RW (SFR1_BASE + 0x31*4)
- #define SDADCDMAFLAG SFR_RW (SFR1_BASE + 0x32*4)
- #define SDADCLDMAADDR SFR_RW (SFR1_BASE + 0x33*4)
- #define SDADCLDMASIZE SFR_RW (SFR1_BASE + 0x34*4)
- #define SDADCRDMAADDR SFR_RW (SFR1_BASE + 0x35*4)
- #define SDADCRDMASIZE SFR_RW (SFR1_BASE + 0x36*4)
- #define SDADCDIGCON SFR_RW (SFR1_BASE + 0x37*4)
- #define SDADCGAINCON SFR_RW (SFR1_BASE + 0x38*4)
- #define SDADCBFCON SFR_RW (SFR1_BASE + 0x39*4)
- #define SDADCBFKICK SFR_RW (SFR1_BASE + 0x3a*4)
- #define SDADCBFCOEF SFR_RW (SFR1_BASE + 0x3b*4)
- #define AUANGCON0 SFR_RW (SFR1_BASE + 0x3c*4)
- #define AUANGCON1 SFR_RW (SFR1_BASE + 0x3d*4)
- #define AUANGCON2 SFR_RW (SFR1_BASE + 0x3e*4)
- #define AUANGCON3 SFR_RW (SFR1_BASE + 0x3f*4)
- //------------------------- SFR Group5 ---------------------------------------//
- #define IISCON0 SFR_RW (SFR5_BASE + 0x00*4)
- #define IISBAUD SFR_RW (SFR5_BASE + 0x01*4)
- #define IISDMACNT SFR_RW (SFR5_BASE + 0x02*4)
- #define IISDMAOADR0 SFR_RW (SFR5_BASE + 0x03*4)
- #define IISDMAOADR1 SFR_RW (SFR5_BASE + 0x04*4)
- #define IISDMAIADR0 SFR_RW (SFR5_BASE + 0x05*4)
- #define IISDMAIADR1 SFR_RW (SFR5_BASE + 0x06*4)
- #define FMRXDGTCON0 SFR_RW (SFR5_BASE + 0x07*4)
- #define FMRXKICK SFR_RW (SFR5_BASE + 0x08*4)
- #define FMRXFLAG SFR_RW (SFR5_BASE + 0x09*4)
- #define FMRXDCSUM SFR_RW (SFR5_BASE + 0x0a*4)
- #define FMRXRSSISUM SFR_RW (SFR5_BASE + 0x0b*4)
- #define FMRXRSSIPOW SFR_RW (SFR5_BASE + 0x0c*4)
- #define FMRXPILOTPOW SFR_RW (SFR5_BASE + 0x0d*4)
- #define FMRXBALANVOL SFR_RW (SFR5_BASE + 0x0e*4)
- #define FMRXZEROCROSSCON SFR_RW (SFR5_BASE + 0x0f*4)
- #define GPDMACON SFR_RW (SFR5_BASE + 0x10*4)
- #define GPDMAADDRST0 SFR_RW (SFR5_BASE + 0x11*4)
- #define GPDMAADDRST1 SFR_RW (SFR5_BASE + 0x12*4)
- #define GPDMAKICK SFR_RW (SFR5_BASE + 0x13*4)
- #define FMRXDAMADDR SFR_RW (SFR5_BASE + 0x14*4)
- #define FMRXDMASIZE SFR_RW (SFR5_BASE + 0x15*4)
- #define FMRXDMACON SFR_RW (SFR5_BASE + 0x16*4)
- #define FMRXDMAFLAG SFR_RW (SFR5_BASE + 0x17*4)
- #define FMRXANGCON0 SFR_RW (SFR5_BASE + 0x18*4)
- #define FMRXANGCON1 SFR_RW (SFR5_BASE + 0x19*4)
- #define FMRXANGCON2 SFR_RW (SFR5_BASE + 0x1a*4)
- #define FMRXANGCON3 SFR_RW (SFR5_BASE + 0x1b*4)
- #define FMRXPLLDIGCON SFR_RW (SFR5_BASE + 0x1c*4)
- #define FMRXADCPLLDIV SFR_RW (SFR5_BASE + 0x1d*4)
- #define FMRXLOPLLDIV SFR_RW (SFR5_BASE + 0x1e*4)
- #define FMRXZEROCROSSCNT SFR_RW (SFR5_BASE + 0x1f*4)
- #define SADCDAT0 SFR_RO (SFR5_BASE + 0x20*4)
- #define SADCDAT1 SFR_RO (SFR5_BASE + 0x21*4)
- #define SADCDAT2 SFR_RO (SFR5_BASE + 0x22*4)
- #define SADCDAT3 SFR_RO (SFR5_BASE + 0x23*4)
- #define SADCDAT4 SFR_RO (SFR5_BASE + 0x24*4)
- #define SADCDAT5 SFR_RO (SFR5_BASE + 0x25*4)
- #define SADCDAT6 SFR_RO (SFR5_BASE + 0x26*4)
- #define SADCDAT7 SFR_RO (SFR5_BASE + 0x27*4)
- #define SADCDAT8 SFR_RO (SFR5_BASE + 0x28*4)
- #define SADCDAT9 SFR_RO (SFR5_BASE + 0x29*4)
- #define SADCDAT10 SFR_RO (SFR5_BASE + 0x2a*4)
- #define SADCDAT11 SFR_RO (SFR5_BASE + 0x2b*4)
- #define SADCDAT12 SFR_RO (SFR5_BASE + 0x2c*4)
- #define SADCDAT13 SFR_RO (SFR5_BASE + 0x2d*4)
- #define SADCDAT14 SFR_RO (SFR5_BASE + 0x2e*4)
- #define SADCDAT15 SFR_RO (SFR5_BASE + 0x2f*4)
- #define SADCCON SFR_RW (SFR5_BASE + 0x30*4)
- #define SADCCH SFR_RW (SFR5_BASE + 0x31*4)
- #define SADCST SFR_WO (SFR5_BASE + 0x32*4)
- #define SADCBAUD SFR_WO (SFR5_BASE + 0x33*4)
- #define MBISTCON SFR_WO (SFR5_BASE + 0x34*4)
- #define MBISTEADR SFR_WO (SFR5_BASE + 0x35*4)
- #define MBISTBADR SFR_WO (SFR5_BASE + 0x36*4)
- #define MBISTCRC SFR_WO (SFR5_BASE + 0x37*4)
- #define MBISTERR SFR_WO (SFR5_BASE + 0x38*4)
- #define WKUPCON SFR_WO (SFR5_BASE + 0x39*4)
- #define WKUPEDG SFR_WO (SFR5_BASE + 0x3a*4)
- #define WKUPCPND SFR_WO (SFR5_BASE + 0x3b*4)
- //#define FMRXLOAFCCON SFR_RW (SFR5_BASE + 0x3c*4)
- #define EFCON0 SFR_RW (SFR5_BASE + 0x3d*4)
- #define EFCON1 SFR_WO (SFR5_BASE + 0x3e*4)
- #define EFDAT SFR_RW (SFR5_BASE + 0x3f*4)
- //------------------------- SFR Group6 ---------------------------------------//
- #define GPIOASET SFR_RW (SFR6_BASE + 0x00*4)
- #define GPIOACLR SFR_RW (SFR6_BASE + 0x01*4)
- #define GPIOA SFR_RW (SFR6_BASE + 0x02*4)
- #define GPIOADIR SFR_RW (SFR6_BASE + 0x03*4)
- #define GPIOADE SFR_RW (SFR6_BASE + 0x04*4)
- #define GPIOAFEN SFR_RW (SFR6_BASE + 0x05*4)
- #define GPIOADRV SFR_RW (SFR6_BASE + 0x06*4)
- #define GPIOAPU SFR_RW (SFR6_BASE + 0x07*4)
- #define GPIOAPD SFR_RW (SFR6_BASE + 0x08*4)
- #define GPIOAPU200K SFR_RW (SFR6_BASE + 0x09*4)
- #define GPIOAPD200K SFR_RW (SFR6_BASE + 0x0a*4)
- #define GPIOAPU300 SFR_RW (SFR6_BASE + 0x0b*4)
- #define GPIOAPD300 SFR_RW (SFR6_BASE + 0x0c*4)
- #define GPIOAMFUNC SFR_RW (SFR6_BASE + 0x0f*4)
- #define GPIOBSET SFR_RW (SFR6_BASE + 0x10*4)
- #define GPIOBCLR SFR_RW (SFR6_BASE + 0x11*4)
- #define GPIOB SFR_RW (SFR6_BASE + 0x12*4)
- #define GPIOBDIR SFR_RW (SFR6_BASE + 0x13*4)
- #define GPIOBDE SFR_RW (SFR6_BASE + 0x14*4)
- #define GPIOBFEN SFR_RW (SFR6_BASE + 0x15*4)
- #define GPIOBDRV SFR_RW (SFR6_BASE + 0x16*4)
- #define GPIOBPU SFR_RW (SFR6_BASE + 0x17*4)
- #define GPIOBPD SFR_RW (SFR6_BASE + 0x18*4)
- #define GPIOBPU200K SFR_RW (SFR6_BASE + 0x19*4)
- #define GPIOBPD200K SFR_RW (SFR6_BASE + 0x1a*4)
- #define GPIOBPU300 SFR_RW (SFR6_BASE + 0x1b*4)
- #define GPIOBPD300 SFR_RW (SFR6_BASE + 0x1c*4)
- #define GPIOESET SFR_RW (SFR6_BASE + 0x20*4)
- #define GPIOECLR SFR_RW (SFR6_BASE + 0x21*4)
- #define GPIOE SFR_RW (SFR6_BASE + 0x22*4)
- #define GPIOEDIR SFR_RW (SFR6_BASE + 0x23*4)
- #define GPIOEDE SFR_RW (SFR6_BASE + 0x24*4)
- #define GPIOEFEN SFR_RW (SFR6_BASE + 0x25*4)
- #define GPIOEDRV SFR_RW (SFR6_BASE + 0x26*4)
- #define GPIOEPU SFR_RW (SFR6_BASE + 0x27*4)
- #define GPIOEPD SFR_RW (SFR6_BASE + 0x28*4)
- #define GPIOEPU200K SFR_RW (SFR6_BASE + 0x29*4)
- #define GPIOEPD200K SFR_RW (SFR6_BASE + 0x2a*4)
- #define GPIOEPU300 SFR_RW (SFR6_BASE + 0x2b*4)
- #define GPIOEPD300 SFR_RW (SFR6_BASE + 0x2c*4)
- #define GPIOFSET SFR_RW (SFR6_BASE + 0x30*4)
- #define GPIOFCLR SFR_RW (SFR6_BASE + 0x31*4)
- #define GPIOF SFR_RW (SFR6_BASE + 0x32*4)
- #define GPIOFDIR SFR_RW (SFR6_BASE + 0x33*4)
- #define GPIOFDE SFR_RW (SFR6_BASE + 0x34*4)
- #define GPIOFFEN SFR_RW (SFR6_BASE + 0x35*4)
- #define GPIOFDRV SFR_RW (SFR6_BASE + 0x36*4)
- #define GPIOFPU SFR_RW (SFR6_BASE + 0x37*4)
- #define GPIOFPD SFR_RW (SFR6_BASE + 0x38*4)
- #define GPIOFPU200K SFR_RW (SFR6_BASE + 0x39*4)
- #define GPIOFPD200K SFR_RW (SFR6_BASE + 0x3a*4)
- #define GPIOFPU300 SFR_RW (SFR6_BASE + 0x3b*4)
- #define GPIOFPD300 SFR_RW (SFR6_BASE + 0x3c*4)
- //------------------------- SFR Group7 ---------------------------------------//
- #define GPIOGSET SFR_RW (SFR7_BASE + 0x00*4)
- #define GPIOGCLR SFR_RW (SFR7_BASE + 0x01*4)
- #define GPIOG SFR_RW (SFR7_BASE + 0x02*4)
- #define GPIOGDIR SFR_RW (SFR7_BASE + 0x03*4)
- #define GPIOGDE SFR_RW (SFR7_BASE + 0x04*4)
- #define GPIOGFEN SFR_RW (SFR7_BASE + 0x05*4)
- #define GPIOGDRV SFR_RW (SFR7_BASE + 0x06*4)
- #define GPIOGPU SFR_RW (SFR7_BASE + 0x07*4)
- #define GPIOGPD SFR_RW (SFR7_BASE + 0x08*4)
- #define GPIOGPU200K SFR_RW (SFR7_BASE + 0x09*4)
- #define GPIOGPD200K SFR_RW (SFR7_BASE + 0x0a*4)
- #define GPIOGPU300 SFR_RW (SFR7_BASE + 0x0b*4)
- #define GPIOGPD300 SFR_RW (SFR7_BASE + 0x0c*4)
- #define IRRXCON SFR_RW (SFR8_BASE + 0x1b*4)
- #define IRRXDAT SFR_RW (SFR8_BASE + 0x1c*4)
- #define IRRXCPND SFR_WO (SFR8_BASE + 0x1d*4)
- #define IRRXERR0 SFR_WO (SFR8_BASE + 0x1e*4)
- #define IRRXERR1 SFR_WO (SFR8_BASE + 0x1f*4)
- #define USERKEY SFR_RW (SFR8_BASE + 0x20*4)
- #define PROTCON1 SFR_RW (SFR8_BASE + 0x21*4)
- //------------------------- SFR Group9 ---------------------------------------//
- #define TMR3CON SFR_RW (SFR9_BASE + 0x00*4)
- #define TMR3CPND SFR_WO (SFR9_BASE + 0x01*4)
- #define TMR3CNT SFR_RW (SFR9_BASE + 0x02*4)
- #define TMR3PR SFR_RW (SFR9_BASE + 0x03*4)
- #define TMR3CPT SFR_RO (SFR9_BASE + 0x04*4)
- #define TMR3DUTY0 SFR_WO (SFR9_BASE + 0x05*4)
- #define TMR3DUTY1 SFR_WO (SFR9_BASE + 0x06*4)
- #define TMR3DUTY2 SFR_WO (SFR9_BASE + 0x07*4)
- #define TMR4CON SFR_RW (SFR9_BASE + 0x08*4)
- #define TMR4CPND SFR_WO (SFR9_BASE + 0x09*4)
- #define TMR4CNT SFR_RW (SFR9_BASE + 0x0a*4)
- #define TMR4PR SFR_RW (SFR9_BASE + 0x0b*4)
- #define TMR4CPT SFR_RO (SFR9_BASE + 0x0c*4)
- #define TMR4DUTY0 SFR_WO (SFR9_BASE + 0x0d*4)
- #define TMR4DUTY1 SFR_WO (SFR9_BASE + 0x0e*4)
- #define TMR4DUTY2 SFR_WO (SFR9_BASE + 0x0f*4)
- #define TMR5CON SFR_RW (SFR9_BASE + 0x10*4)
- #define TMR5CPND SFR_WO (SFR9_BASE + 0x11*4)
- #define TMR5CNT SFR_RW (SFR9_BASE + 0x12*4)
- #define TMR5PR SFR_RW (SFR9_BASE + 0x13*4)
- #define TMR5CPT SFR_RO (SFR9_BASE + 0x14*4)
- #define TMR5DUTY0 SFR_WO (SFR9_BASE + 0x15*4)
- #define TMR5DUTY1 SFR_WO (SFR9_BASE + 0x16*4)
- #define TMR5DUTY2 SFR_WO (SFR9_BASE + 0x17*4)
- #define UART2CON SFR_RW (SFR9_BASE + 0x18*4)
- #define UART2CPND SFR_WO (SFR9_BASE + 0x19*4)
- #define UART2BAUD SFR_RW (SFR9_BASE + 0x1a*4)
- #define UART2DATA SFR_RW (SFR9_BASE + 0x1b*4)
- #define PORTINTEDG SFR_RW (SFR9_BASE + 0x1e*4)
- #define PORTINTEN SFR_RW (SFR9_BASE + 0x1f*4)
- #define SPI1CON SFR_RW (SFR9_BASE + 0x20*4)
- #define SPI1BUF SFR_RW (SFR9_BASE + 0x21*4)
- #define SPI1BAUD SFR_RW (SFR9_BASE + 0x22*4)
- #define SPI1CPND SFR_RW (SFR9_BASE + 0x23*4)
- #define SPI1DMACNT SFR_RW (SFR9_BASE + 0x24*4)
- #define SPI1DMAADR SFR_RW (SFR9_BASE + 0x25*4)
- #define RTCALM SFR_RW (SFR9_BASE + 0x2e*4)
- #define RTCCNT SFR_RW (SFR9_BASE + 0x2f*4)
- #define RTCCON0 SFR_RW (SFR9_BASE + 0x30*4)
- #define RTCCON1 SFR_RW (SFR9_BASE + 0x31*4)
- #define RTCCON2 SFR_RW (SFR9_BASE + 0x32*4)
- #define RTCCON3 SFR_RW (SFR9_BASE + 0x33*4)
- #define RTCCON4 SFR_RW (SFR9_BASE + 0x34*4)
- #define RTCCON5 SFR_RW (SFR9_BASE + 0x35*4)
- #define RTCCON6 SFR_RW (SFR9_BASE + 0x36*4)
- #define RTCCON7 SFR_RW (SFR9_BASE + 0x37*4)
- #define RTCCON8 SFR_RW (SFR9_BASE + 0x38*4)
- #define RTCCON9 SFR_RW (SFR9_BASE + 0x39*4)
- #define RTCCON10 SFR_RW (SFR9_BASE + 0x3a*4)
- #define RTCCON11 SFR_RW (SFR9_BASE + 0x3b*4)
- #define RTCCON12 SFR_RW (SFR9_BASE + 0x3c*4)
- #define RTCCON13 SFR_RW (SFR9_BASE + 0x3d*4)
- #define RTCCON14 SFR_RW (SFR9_BASE + 0x3e*4)
- #define RTCCON15 SFR_RW (SFR9_BASE + 0x3f*4)
- //------------------------- SFR Group10 --------------------------------------//
- #define TKIE SFR_RW (SFR10_BASE + 0x00*4)
- #define TKCPND SFR_RW (SFR10_BASE + 0x01*4)
- #define TKCON SFR_RW (SFR10_BASE + 0x02*4)
- #define TKACON SFR_RW (SFR10_BASE + 0x03*4)
- #define TKCNT SFR_RW (SFR10_BASE + 0x04*4)
- #define TKCDPR0 SFR_RW (SFR10_BASE + 0x05*4)
- #define TKCDPR1 SFR_RW (SFR10_BASE + 0x06*4)
- #define TKTMR SFR_RW (SFR10_BASE + 0x07*4)
- #define TKBCNT SFR_RW (SFR10_BASE + 0x09*4)
- #define TKPTHD SFR_RW (SFR10_BASE + 0x0a*4)
- #define TKETHD SFR_RW (SFR10_BASE + 0x0b*4)
- #define PIANOCON SFR_RW (SFR10_BASE + 0x10*4)
- #define PIANOBUF SFR_WO (SFR10_BASE + 0x11*4)
- #define TONEDLY SFR_RW (SFR10_BASE + 0x12*4)
- #define TONEDLY1 SFR_RW (SFR10_BASE + 0x13*4)
- //------------------------- others --------------------------------------//
- #define MEMCON1 SFR_RW (SFR10_BASE + 0x2e*4)
- #define MEMCON2 SFR_RW (SFR10_BASE + 0x2f*4)
- #endif
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